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[USB develop] pci-verilog

Description: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Platform: | Size: 431104 | Author: tom | Hits:

[VHDL-FPGA-Verilog] opencore_crt

Description: 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
Platform: | Size: 683008 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[VHDL-FPGA-Verilog] pci

Description: pci总线源代码，总线设计参考。适合于飓风系列FPGA设计参考。-pci bus source code, the bus design. For hurricane series FPGA design.
Platform: | Size: 23552 | Author: Zeng.q | Hits:

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